Quiz submission record for quiz5-2-2 at Thu Jul 22 10:54:17 2004:

Your Answer for Question 1:
The branch delay slot is used to store the next instruction to  be executed after a branch.  It can store the instruction that is the branch address of the branch or it can store the instruction before the branch depending on the prediction that the processor makes.

Your Answer for Question 2:
It can't run at full speed because one of the source operands in the second instruction depends on the target operand of the first instruction.  Thus, the second instruction is delayed three stages so that it can get the value from the register $t0.  We can fix this stall in the pipeline by connecting the output of the memory lookup of the first instruction to on of the inputs of the adder ALU of the second instruction. This way, we would only be delayed by 1 stage, rather than 3.

Your Answer for Question 3:
We will encounter a structural hazard because the first and fourth instruction would be accessing the same memory assuming they are either strore or load operations.


Your unique submission ID is quiz5-2-2-cs61c-ee-1090518857-1634.