Quiz submission record for quiz5-2-2 at Wed Jul 21 21:16:17 2004:

Your Answer for Question 1:
One way of dealing with control hazards is using a delayed decision. The MIPS architecture implements delayed branches, which means that the delayed branch always executes the next sequential instruction, with the branch taking place -after- that one instruction delay. Basically, if a branch is taken, the next instruction is the branch target address. Otherwise, the next instruction is just the PC + 4. A branch delay slot contains the instruction that is executed after a delayed branch instruction. The reason for the delayed branch slot is to account for the need that we need to know whether or not a branch is taken or not taken in advance before the next instruction in the pipeline starts. 

Your Answer for Question 2:
The reason the sequence of instructions cannot run at full speed on the pipelined datapath without special hardware is because the add instruction depends on the value of $t0, which is obtained only at the very end of the lw instruction (data hazard). To solve this, we would need to not only forward the value of $t0 from the lw instruction to the add instruction but also stall. The reason for this is because the value of $t0 is available only after the fourth stage of the lw instruction, which is too late for the input of the third stage of add. 

Your Answer for Question 3:
This would break our pipelining scheme because we would be traveling backwards when trying to access data memory since that occurs at a later stage in the pipeline. This would make reading files from registers and retrieving data from memory extremely complicated since we would need to separate stages out so that these processes are happening independently (so we are not washing the same load twice, missing loads, etc.) 


Your unique submission ID is quiz5-2-2-cs61c-ei-1090469777-3319.