Quiz submission record for quiz5-2-2 at Thu Jul 22 00:35:24 2004:

Your Answer for Question 1:
A branch delay slot is a delay that starts when a conditional is being evaluated but before it is completed, and before the branch address is figured out.

If you don't know where to branch, then why do work?  What if you end up doing something that takes up extra cpu cycles when that's not the correct way to branch?

Your Answer for Question 2:
lw needs to load something from memory and we don't know how long that could take.  

Hardware: Make the memory faster.

Software: Make a better compiler.  Hire a better MIPS programmer.


Your Answer for Question 3:
Assuming that the order is Instruction fetch, Reg, ALU, Data access, Reg, if we have more than three instructions being executed per clock cycle, Instruction fetch and Data access will be run at the same time.  Therefore if there were only 1 memory module, it wouldn't work because that memory module would be used by instruction fetch and data access in the same clock cycle and that's not really possible.


Your unique submission ID is quiz5-2-2-cs61c-ej-1090481724-959.