Quiz submission record for quiz5-2-2 at Thu Jul 22 01:35:06 2004:

Your Answer for Question 1:
A branch delay slot is where you insert an instruction between calculating a branch, and calculating the statement that follows it (or what it branches too).  Since when you calculate a branch, you will not reach whether the branch should be followed until the ALU, there is a stall of one cycle between evaluating a branch, and to start evaluating the instruction it should follow.  This is solved by a branch delay slot, in which a statement which can be evaluated both before and after the branch is inserted, so that there will not be a stall between evaluating a branch, and evaluating its next instruction; the time is not wasted, but is instead used by the instruction in the branch delay slot.

Your Answer for Question 2:
It is because the new value of $t0 used in the add statement will not be actually stored in memory until the last stage of the load word pipeline, which is writing to a register.  This penalty can be reduced by forwarding, which sends the value needed to the add instruction after it has been calculated by the reading from memory stage.

Your Answer for Question 3:
It will break our scheme because we will need to access the same memory with different instructions simultaneously.  We will be writing and reading to the same block of memory, which will cause problems because the values stored there will not have a chance to stabilize.


Your unique submission ID is quiz5-2-2-cs61c-el-1090485306-903.