Quiz submission record for quiz5-2-2 at Wed Jul 21 22:56:58 2004:

Your Answer for Question 1:
It's a time slot when a branch statement is executed.
In pipelining, the control may jump to the next instruction before branch is taken. A branch delay slot delays the control and thus prevent this problem

Your Answer for Question 2:
It's because add has to wait for the result for $t0 from lw.

We can use forwarding or bypassing scheme to resolve this problem. That is, once the the value of $to is obtained, it is directly forwarded to add to finish the execution

Your Answer for Question 3:
If we only have a single memory, then when an instruction is accessing data from memory while another instruction is fretching instruction from the same memory, the pipelining scheme will break.


Your unique submission ID is quiz5-2-2-cs61c-en-1090475818-1999.