Quiz submission record for quiz5-2-2 at Wed Jul 21 23:20:18 2004:

Your Answer for Question 1:
When faced with a branch, we cannot go through the datapath as fast as we do with other instructions (like add). This is because we are not sure if we should branch or not, so this causes some delay in the pipeline. One solution to this is to use the branch delay slot, which puts the next sequential instruction (that does not affect the branch) into the delayed branch slot. The delayed branch always exectues the next sequential instruction, with the branch taking place after that one instruction delay. The purpose of this is to limit pipeline delays.

Your Answer for Question 2:
This cannot run at full speed because the add requires the value of $t0, which is being loaded at 0($s1) in the previous instruction, so we cannot add until the lw finishes. One possibility is to hardwire the value from 0($s1) into the ALU we add into right after we find it, but this would require some more control signals.

Your Answer for Question 3:
This will break the pipelining scheme since because every instruction will require use of data, we cannot start using pipelining to do another instruction because that would require us to use the now combined instruction/data memory module. But since we need data for the current instruction, we cannot load the next one, so we cannot pipeline.


Your unique submission ID is quiz5-2-2-cs61c-ev-1090477218-3066.