Quiz submission record for quiz5-2-2 at Thu Jul 22 01:33:55 2004:

Your Answer for Question 1:
It is a slot in pipelining scheme between the execution of branch instruction and the following instruction (which is determined by the branch instruction), in which an unrelated instruction is inserted.
Without the utilization of this slot, the processor will be much slower because it has to stall until the next PC is determined according to the branch instruction. By inserting something unaffected here, we save time and achieve normal pipeline speed.

Your Answer for Question 2:
These instructions cannot be pipelined straightforwardly because the second instruction uses t0 which is determined in the first instruction. To reduce this penalty,
(1) Implement new wire so that the memory fetched from lw instruction can go directly into ALU unit so that the second instruction can be executed ASAP.
(2) Come up with a software solution which inserts an unrelated instruction inbetween this bubble, similar to what we do with brach delay slots.

Your Answer for Question 3:
Having only one memory module means that each instruction has to spend two stages at this memory module (IF and WB). Normally, each instruction has to spend only one stage at each memory module.
This means that in our pipelining scheme, the next instruction in line has to wait for two stages instead of one, so it will half the speed of our processor.


Your unique submission ID is quiz5-2-2-cs61c-ew-1090485235-2572.