Quiz submission record for quiz5-2-2 at Thu Jul 22 10:24:51 2004:

Your Answer for Question 1:
It's a instruction line following the branch.
it's a solution to control hazard in which MIPS software will place an instruction immediately after the delayed branch instruction that is not affected by the branch,and a taken branch changes the address of the instruction that follows this safe instruction.

Your Answer for Question 2:
because the value in $t0 is available only after the fourth stage of the first instruction in the dependence, which is too late for the input of the third stage of add. so even with forwarding we have to
stall one stage.
we can put a nop after lw to be able to use forwarding.
By adding a multiplexer to the input of the ALU and with proper controls,we can run pipelines at full speed.

Your Answer for Question 3:
because in 1 clock cycle that the first instruction is 
accessing data from memory,the following for instance 
fourth instruction is fetching an instruction from that
same memory.With out two memories, out pipeline could have a structural hazard.


Your unique submission ID is quiz5-2-2-cs61c-fx-1090517091-2499.