Answer from cs61c-el (David Tung 16479725) for Question 1
The problem would be that in our original single-cycle processor, all of the control was decided during the instruction decode stage.  This worked in our original processor because a single-cycle for it was to let a single instruction propagate and finish through the whole datapath before sending another instruction through.  This will no longer work in a pipelined datatpath.  Each instruction that is currently in the datapath has its own control values, and for the stage that it is in, it needs the control values specific to the instruction that it represents.  Therefore, they need to carry along their values.  For example, suppose we had an add instruction that was in the writeback stage, and a branch instruction in the instruction decode stage.  Without pipelining the control, the write enable to the regfile would be turned off, and the value from our add instruction would not be written into its register.