Answer from cs61c-ew (Joo-Rak Son 16103505) for Question 1
Then the execution of code will get all jumbled up together and you will not get the behavior you desired. For example, PC would be incrementing by 4 even when the branch should have been taken (which will notify the PC Mux after EX/MEM stage), so in this case two unnecessary instructions will be processed. Another instance would be read after write data dependency. For instructions like add $1, $2, $3 and add $4, $1, $1, the register $1's value is not settled until the WB stage, so the second instruction will be using $1's old value instead of the new. Store and load instructions in a row present the similar problem.