Quiz submission record for quiz6-1-1 at Mon Jul 26 01:17:58 2004:

Your Answer for Question 1:
The control signals for each stage would not necessarally be the correct controls for the instruction that is being processed in the stage.


Your Answer for Question 2:
the inputs come from the Memory Access (normal), data memory(forwarded from pervious instruction), or writeback (forwarded from previous instruction) sections.
The first case is used in not fowarded situations.
The second case would be used in:
add $3 $2 $5
add $6 $3 $7 
because it would need to get $3 from the ALU of the last instruction.  The ALU from the last instruction is in the memory phase in this instruction.
The third case would be used in:
lw $3 0($4)
add $2 $3 $5
because it would need the value loaded from memory in the previous instruction. 

Your Answer for Question 3:
A hazard unit simply instructs the stages effected to do the same instruction twice.  This is done by not incrementing the PC or the IF/ID regester.  

The hazard will not do this over and over because the unit checks the dependancy on each stage, so eventually, the dependancy will be resolve.  Mathematically, it is sure to have been resolved in 5 cycles because all previous instructions will have been fully executed.



Your unique submission ID is quiz6-1-1-cs61c-au-1090829878-2087.