Quiz submission record for quiz6-1-1 at Mon Jul 26 10:52:05 2004:

Your Answer for Question 1:
The processor could not function correctly because signals from ID need to be propagated to the EX state (the ALU). Also the write register needs to be propagated back and the memory control and register write back control would fail.

Your Answer for Question 2:
The muxes select between the value being passed from the pipleine registers, value being written back in the WB stage (MEM/WB) and the value being written to the data memory (EX/MEM).

Passing value down the pipleine (no forwarding):
add $t0 $t1 $t2
sub $t3 $t4 $t5

Passing from EX/MEM:
add *$t0* $t1 $t2
sub $t5 *$t0* $t6

Passing from EX/MEM:
add *$t0* $t1 $t2
sub $t3 $t4 $t8
sub $t5 *$t0* $t6

Your Answer for Question 3:
It inserts a noop to the ex stage, turns off the nextPC update and turns off InstReg update, so the same instruction is refetech and redecoded.

As long as you turn on the nextPC and InstReg logic the next clock cycle, the pipleine will continue functioning as usual.


Your unique submission ID is quiz6-1-1-cs61c-cm-1090864325-3266.