Quiz submission record for quiz6-1-1 at Sun Jul 25 23:58:33 2004:

Your Answer for Question 1:
If we simply pipelined the datapath without the control, the new processor would not work because not only does the data need to be passed along through the clock cycles of each instruction but control signals must also do the same. This is so that the control values of one instruction will not be overwritten by the control values of a consecutive instruction when going through the pipeline. Control signals are spread out through the entire processor and those signals must remain the same for every instruction, or else there is no guarantee on the results. 


Your Answer for Question 2:
The purpose of the muxes are so that any needed data can be forwarded from any pipeline register (to avoid data hazards). The three possible values come from either the register file values or one of the forwarded values (from EX/MEM or MEM/WB).  

add $s0, $t0, $0 
- $t0 would be read from the register file

add $t0, $t1, $t2
add $t2, $t0, $t0 
- The value of $t0 will be forwarded from EX/MEM. 

lw $t0, 0($t1)
sll $0, $0, 0         #nop
add $t1, $t0, $t0 
- The value of $t0 will be forwarded from MEM/WB 


Your Answer for Question 3:
The hazard detection unit operations during the ID stage so that it can insert a stall between the load and its use. It first tests to see if the instruction is a load since the only instruction that reads data memory is a load. It then checks to see if the destination register field of the load in the EX stage matches either source register of the instruction in the ID stage. If this is true, then the instruction stalls 1 clock cycle. The fact that one stall essentially is like the equivalent of adding a nop (sll $0, $0, 0) and shifts all other instructions down prevents the hazard unit from repeatedly inserting the same bubble. 


Your unique submission ID is quiz6-1-1-cs61c-ei-1090825113-2397.