Quiz submission record for quiz6-1-1 at Mon Jul 26 10:14:16 2004:

Your Answer for Question 1:
As for the single-cycle implementation, there is no separate write signal for PC,so by the same argument, there are no separate write signals for the pipeline registers.

Your Answer for Question 2:
each of inputs are coming from each pipeline to forward.

add $1, $1, $2
add $1, $1, $3
add $1, $1, $4
...


Your Answer for Question 3:
By identifying the hazard in the ID stage, we can insert a bubble into the pipeline by changing the EX,MEM,and WB control fields of the ID/EX pipeline register to 0.

As inserting the bubbles, there are no data hazards.


Your unique submission ID is quiz6-1-1-cs61c-em-1090862056-2947.