Quiz submission record for quiz6-1-1 at Mon Jul 26 09:59:11 2004:

Your Answer for Question 1:
The control signals would be sent at improper times. As new instructions enter the ID stage, different control signals would be sent and the old ones would be overwritten. writeEnable might no longer be asserted and a desired memory write might not occur.

Your Answer for Question 2:
These are 1) rt from the regfile, 2) result of a memory read from the MEM/WB register and 3) result of an ALU operation from the EX/MEM register.

1) add  $2, $3, $1
2) lw   $2, 0($1)
   add  $3, $2, $1
3) add  $2, $3, $1
   sub  $3, $2, $1

Your Answer for Question 3:
All control signals are deasserted so nothing is done during that cycle. A hazard detection unit is added to select between actual control values and deasserted control values; previous control values are restored after there is no longer a hazard.


Your unique submission ID is quiz6-1-1-cs61c-eq-1090861151-2682.