Quiz submission record for quiz6-1-1 at Sun Jul 25 20:01:31 2004:

Your Answer for Question 1:
If we did not pipeline control, we would cause unpredictable results in our datapath. As one instruction is going through the datapath, another instruction may be running in parallel (although a cycle behind). However, the control signals for that new instruction will override the signals for the first instruction, so the first instruction, which may have been an innocent nop of all things, could actually end up doing addition or writing something to memory/registers. Basically, each new instruction's control signals will override the previous instruction's signals, causing the previous instructions to work improperly.

Your Answer for Question 2:
The three values are coming from the register file, a prior ALU result, or data memory/an earlier ALU result.

register file value:

add $1, $2, $3 (where $2 or $3 do not cause data hazards).

prior ALU result:

sub $2, $1, $3
and $12, $2, $5

data memory/earlier ALU result:

add $1, $1, $2
add $1, $1, $3
add $1, $1, $4

Your Answer for Question 3:
The hazard unit insert bubbles using a hazard detection unit. It first checks to see if the instruction is a load (which is the only instruction that could cause a stall). Then it checks to see if the destination register field of the load in the EX stage matches either source register of the instruction in the ID stage. If the condition holds, the instruction stalls 1 clock cycle.

The hazard unit avoids inserting the same bubble over and over by the checks in the detection unit. Then it knows after the stall that forwarding is possible, so there is no need to continually bubble.


Your unique submission ID is quiz6-1-1-cs61c-ev-1090810891-3030.