Quiz submission record for quiz6-2-2 at Wed Jul 28 20:59:55 2004:

Your Answer for Question 1:
EPC holds an address of the instruction that caused the exception.
Cause holds exception type and pending interrupt bits.
Accessed by lwc0, mfc0, mtc0, swc0

Your Answer for Question 2:
wrong exception address is stored in the EPC in pipelined computer

Your Answer for Question 3:
Can waist a lot of processor time, since IO devices are so  slow, that processor will have data ready many times, before IO gets to it.

Your Answer for Question 4:
In order for the processor to address the IO device, it uses memory-mapped io: portions of address space are assigned to IO dedvices and reads and writes to those addresses are interpreted as as commands to IO devices.
     
      lui $t0, 0xffff  # load addr. of rec.control
loop: lw $t1, 0($t0)   # store control
      sll $t1, $t1, 31 # erase 31-1 bits
      srl $t1, $t1, 31 # now only status bit is there
      beqz $t1, loop   # keep looping if not ready
      add $v0, $t1, $0 # otherwise return result 


Your unique submission ID is quiz6-2-2-cs61c-bc-1091073595-176.