Quiz submission record for quiz6-2-2 at Thu Jul 29 10:18:27 2004:

Your Answer for Question 1:
EPC holds a 32 bit address of the affected instruction. needed when exceptions are vectored.
Cause register records the cause of an exception. it's also 32 bits although some are unused. 

Your Answer for Question 2:
interrupts or exceptions in pipelined  computers taht are not associated withthe exact instruction that was the cause of the interrupt or exception.

Your Answer for Question 3:
when polling all your doing is going in a loop asking:
is the info ready yet? is the info ready yet..etc,
it's drawback is inefeciency due to a large percentage of the processor used for that one purpose of polling.

Your Answer for Question 4:
it's a scheme inwhich portions of address space are assigned to I/O devices and reads and writes to those addresses are interpretted as commands. 

loop:
      bne $t0, $0, storeBytes
      j loop

storeBytes:
      beq $t1, $0, end
      sb $t1, 0($s2)
      j storeBytes

end 
      addi $v0, $s2, $0
      jr $ra      




Your unique submission ID is quiz6-2-2-cs61c-ch-1091121507-2057.