Answer from cs61c-co (loi dinh 16804224) for Question 1
The exception for TLB entry missing is much more frequent than L1 cache, the operating system loads the TLB from the page table without examining the entry and restarts the instruction when such an exception occurs.  If the entry is avlid, another exception occurs, and the operating system recognizes that a page fault has occurred.  This method makes the frequent case of a TLB miss FAST, at a slight performance penalty for the infrequent case of a page fault.