Quiz submission record for quiz7-1-2 at Tue Aug  3 02:05:32 2004:

Your Answer for Question 1:
The exception for TLB entry missing is much more frequent than L1 cache, the operating system loads the TLB from the page table without examining the entry and restarts the instruction when such an exception occurs.  If the entry is avlid, another exception occurs, and the operating system recognizes that a page fault has occurred.  This method makes the frequent case of a TLB miss FAST, at a slight performance penalty for the infrequent case of a page fault.

Your Answer for Question 2:
 Each tag entry in the TLB holds a portion of the virtual page number and each data entry of the TLB holds a physical page number. Thus the order of the bits does matter in this case, so I think that it would not work


Your unique submission ID is quiz7-1-2-cs61c-co-1091523932-595.