Quiz submission record for quiz7-1-2 at Tue Aug  3 10:19:23 2004:

Your Answer for Question 1:
The miss rate is misses / instructions. Since TLB sizes are typically much, much smaller than L1 caches, and TLB for instructions and data both for four-way set associative. and TLB misses are handled in hardware. then for the same misses, TLB's instrucions are far larger than L1 caches.

Your Answer for Question 2:
In virtual memory, the address usu a vitual page number and a page offset. if we replace the SPN to the right of the SPN, the system will confuse by the offset and SPN. I think it won't work.


Your unique submission ID is quiz7-1-2-cs61c-cq-1091553563-1290.