CS 152
Computer Architecture and Engineering
CS152 Fall 2003
TuTh 2-3:30pm, 306 Soda Hall

Dave Patterson | John Gibson | Jack Kang | Kurt Meinz

News and Calendar | Course Info | Resources | Staff | Webcast | WebNews | WebGrades | Projects
Old News:
11-23-2003 Xilinx Trip!

  • The bus leaves tomorrow at 8:55AM sharp -- we may wait around until 9:00 for stragglers, but after that we are g o n e !
  • This is the current roster for the Xilinx trip. If you are not on it, we don't have you listed as going. If you are listed on it and have changed your mind, please email Jack right away. Also, if you are driving yourself and you are not listed as doing so on the roster, please email Jack as well.
  • We will be meeting outside the 2nd floor of Cory at 8:35 AM on Tuesday 11/25. Please don't be late!! If the TAs wake up early enough, we'll have some donuts on the bus for you guys. We will be arriving at Xilinx at 10 AM, and leaving at approximately 3 PM, arriving back at Berkeley around 4 PM.
  • If you are driving yourself there, please send an email to Jack at cs152-ta@imail.eecs.berkeley.edu so we know who's going where. Please arrive at Xilinx before 10am, and proceed to the lobby of building 1. Directions to Xilinx can be found here. A campus map of Xilinx is here.
11-18-2003 Midterm notes
  • We've posted our notes from today's review section below. These include solutions to the problems.
  • HW4 solutions
11-17-2003 Don't forget to turn in your unfair benchmarks along with your progress reports today, via email to your TA.
11-14-2003 Midterm II is coming up
  • MTII will be held 5:30-8:30pm 11/19/2003 in 1 Leconte
  • The review session will be held during Tuesday's lecture.
  • You are responible for all material covered up to and including Week 12
  • If you can't make the scheduled midterm time, email Kurt immediately.
11-2-2003 The final project is up. Please read it right away.
10-31-2003 HW 4
  • The final HW 4 is up.
  • It is due Tueday 11/18 -- One day later than usual.
11-4-2003 The final project has been updated, and a few more options have been added (write back, explicit register renaming, enhanced superscalar). Additionally, a new grading standard has been added (in red).

For current and future reference, a project working only in simulation but not on board will be graded lower by half a grade to a full grade. This amount will be determined by your TA, based on the reasons for not being able to go to board. If the reasons are for bad design (latches, combinational loop, etc.), then you will lose more points than you would for other, less obvious reasons.

11-4-2003 Design documents for groups that didn't check off by Monday are not due until next Monday, the 10th. However, you are encouraged to turn them in ASAP, so that your TA can look over them early and give you feedback. The website for project proposals is up.
11-3-2003 As Jack mentioned in lab today, lab reports will now be due the midnight of the day following your checkoff day. There will also be checkoffs tomorrow after lecture.
10-29-2003 John will hold office hours today from 2-4, sorry for the short notice.
10-27-2003 Don't forget to e-mail your TA a 1 page "progress report" tonight. This report should contain information such as: what you've completed, what's left to be done, what problems you've ran into, what problems prevented you from completing checkoff last Friday, and what you're going to do to make sure you make checkoff this Friday.
10-22-2003 Solutions and Regrading
  • We've posted a regrading policy on the info page.
  • Solutions and standards for Exam 1 are here.
  • Solutions for HW3 are here.
10-21-2003 Jack's notes for lab 5.
10-20-2003 The memory module has been tested and updated. There is only one minor change:

//always block to assign the data out register after every read
always @(posedge DRAMCLK) begin
    if (RESET)
       data_out <= 32'b0;
    //else if (CurState == read || NextState == waitForProc)
    else if (CurState == read && eight_counter_out == 6)
       data_out <= Data;

The reason this is changed is so that we write in the value being read off immediately, rather than at the end of the read cycle. The datasheets say that the data being read off is guaranteed only for that one cycle, so we must read it in then.
10-19-2003 Just to prevent those of you who may be starting down the wrong path, you may not use dual ported memory for lab 5/6.
10-18-2003 Lab 5/6 has been updated to reflect NEW due dates, along with a note on self-modifying code.

Problem 3, line 2) has been changed from "if either the processor or DRAM is busy with a read-miss" to say "if either the instCache or dataCache is busy with a read-miss."

10-17-2003 Lab 5/6 files are available on M:\
10-10-2003 The dll_standard module has been updated to fix the error that was occuring during translate. Basically, the IBUF module for the reset pad has been commented out. Sorry for the late change. Also, it is probably a good idea to run your processor at a speed much lower than 27MHz the first time around, because many of your designs will not be able to meet a 27Mhz clock cycle.
10-10-2003 Lab 5/6 has been posted for your reading pleasure! Note that the files are not yet available on the M:\, but you can begin to get a sense of what will be required in this lab.
10-12-2003 HW 3 is up.
10-9-2003 This Friday's sections (10/10) have all been cancelled.

Your TA will be communicate with you to set up lab 4 demo times on Monday or Tuesday (10/13-14).

10-9-2003 Your super-motivated TAs stayed up all night to grade your exams:

  • Scores are in glookup.
  • 60 students took the exam.
  • The mean on the exam was 75.3
  • The mean for individual questions was 20.6/30, 27.4/35, and 27.0/35, repsectively.
  • More stats have been posted to the newsgroup.
  • We'll publish solutions shortly.
  • If your login is cs152-cv or cs152-ag and you want a grade for the exam, then you need to log into your class account -- your named account doesn't count.
10-7-2003 HW2 solutions are available.
10-6-2003 Some Lab 4 Files have been modified!

TopLevel.v has been changed to include a line telling synplify where to find all the Xilinx black boxes.

dll_standard.v has been changed also to use CLKDLLE rather than CLKDLL, since we are using the Virtex-E rather than the Virtex architecture.

We have also replaced the clkdll.v file with the clkdlle.v file. Please note that you should not include the clkdlle.v file in your design, the file is only there for your reference. Instead, you should let synplify treat it as a black box, and let Xilinx take care of it during the partition, place, and route.

9-30-2003 Lab 4
  • Lab 4 has been updated, changes have been marked in red.
  • We have extended the Lab 4 demo (checkoff) date to Mon 10/13 (from Fri).
  • We have extended the Lab 4 due date to Tue 10/14 (from Mon).
  • Lab 4 design docs are still due Thursday.
  • 10-6-2003 Midterm 1 is coming up!
    You are responsible for the following readings.
    • Chapter 1: 1.4, 1.5
    • Chapter 2: 2.2-2.6
    • Chapter 3: 3.4-3.9
    • Chapter 4: 4.1, 4.3-4.5
    • Chapter 5: 5.1, 5.3-5.7, 5.8
    • Chapter 6: 6.1-6.7

    The review session used questions from the Spring 2001 and Spring 2003 Midterm. You can find those and other tests here.

    The pipelining question came from the Fall 2003 CS252 prereq exam. You can find that here.

    9-29-2003 Please login to your Unix accounts and complete the registration process!
    • We are going to be entering grades on the Unix systems, so it is important that your information is accurate.
    • Be sure to pick a reasonably secure 'secret code', as this information will be used by the WebGrades system.
    • If you forgot your registration information, or you were never asked for it, log into your Unix account and type 're-register'.
    9-28-2003 John has written a cvs on windows tutorial.
    10-6-2003 If you can't log in to your Unix account because you threw away your account form, email your TA and he will try to recover it for you.
    10-6-2003 Homework 2 has been updated.
    9-28-2003 Kurt is doing OH in the lab today from Noon to about 2:00pm for you lab-3 procrastinators!
    9-26-2003 To clarify Part 3 (Critical Path) of lab 3, what we are looking for is a good discussion of what would be the critical path. What instruction would be the critical path, and why? What assumptions did you have to make (about the speed of certain components relative to others) to come to this conclusion? Explain what would happen if certain modules were much slower than other modules...would a different instruction become the critical path? Trace through the parts of the datapath that the critical path takes.

    Also, please don't forget to include you online notebooks in your lab report, along with a summary at the top of each person's notebook with their total time spent on this lab.

    9-24-2003 Homework 2 is now available. It is long, so please get started as soon as possible.
    9-22-2003 (lec5-1-prs) We have been getting a lot of questions about this, so in the ramblock2048 module, there is a EN signal. This signal simply turns the entire ramblock on and off. For your lab, you will just want to tie this signal to high. The reason that this signal is there is because the ramblock2048 is a more general purpose module than what you will be using it for, and in other designs there may be a reason for turning the entire module off.
    9-20-2003 ALU.v has been updated again. Note that this change has removed the non-blocking statements in favor of blocking statements. If you look carefully at the code, you will see that nonblocking statements in this case will result in the overflow and zero signals being a cycle late. This is one example where blocking ended up being a easier way to describe the circuit than nonblocking. Sorry for the bug, and thanks to the group that found.
    9-19-2003 ALU.v was updated sometime late last night. Make sure you get the new copy (all we did was remove the delay signals, because delays are very difficult to get right in Verilog.) For more information (a lot more) about modeling delay, read this. Please note that this is optional reading, we will not ask that you correctly simulate delays.
    9-15-2003 An explanation of what we want to see in your design docs has been posted in the handouts section. You can also find a sample document there.
    9-15-2003 Lab 3 has been updated! The files are also available on M:\lab3.
    9-18-2003 Because we get about 20 spam messages a day from the cs152@cory.eecs email address, we will not be using it this semester. Email sent to cs152@cory now goes straight to /dev/null. Email addresses for the staff are listed on the Staff page.
    9-15-2003 Please fill out the PRS Survey before Tuesday's lecture if you haven't done so already.
    9-12-2003 We think we have found the problem with the board loading weird values. The problem is that Xilinx Project Navigator needs both the *.EDF netlist from Synplify and the *.NCF contraints file. Without the *.NCF file all the pin location constraints are lost (they are not in the EDIF). Therefore, make sure to copy the *.NCF contraints file to your working directory when you open up Project Navigator again. This may mean that step 2.4 is still valid, although it is untested. Please send feedback on this to us.
    9-12-2003 If you did not get checked off in lab today, you need to make arrangements with your TA. Send them an email with times you are available on Monday and/or Tuesday to set up an appointment. You still need to submit your lab by the 11:59pm deadline on Monday.
    9-12-2003 The submit program is up and working. You can find it in M:\bin. Remember to select Lab 2 and the correct lab section.
    9-11-2003 Many people have been experiencing problems pushing to the board. Hopefully we were able to fix most of these problems today in lab. For those of you who are still having trouble, make sure you do the following
    • Use step 2.4b rather than step 2.4 when going from the synplify edif file. If you have already used step 2.4 in the past, start over by recreating a synplify project and going through the steps using 2.4b.
    • Make sure you use synplify to synthesize. Do not just click Generate Programming File in Xilinx Design Manager with all of your verilog files there. Xilinx Design Manager will not synthezie the pin outs correctly.
    • Check your warnings in synplify! If you have warnings that relate to your logic, that may be your problem
    9-14-2003 Lab 3 is up for your reading pleasure! Please note that the files on the M:\ will not be available until Monday afternoon.
    9-12-2003 Please hold off on submitting your lab until approximately 3pm today. We do have a new version of the submit program, but we have to install it on the computers. An announcement will be made here when we are ready for your submissions.
    9-5-2003 Notes for Jack's Toolflow discussion (Today, 3pm in 119 Cory)
    9-10-2003 A couple of bugs in hw1 have been fixed.
    9-7-2003 Jack's Office Hours for Monday will be from 4-5:30 in lab, not 5-6:30 as earlier stated in lecture.
    9-5-2003 More PRS transmitters are available at the ASUC. Go get yours today!
    9-3-2003 Lab 2 is up!
    • Due to the learning curve, this may be one of the hardest labs of the semester. Get started early! Students who haven't taken 150 should definitely attend the demo on Friday from 3-4pm.
    • The COD Appendices are in the resources page.
    • Jack's Lab 2 overview slides are available.
    9-2-2003 Start working on HW 1.
    • The due date has been extended to Wed 9/10 at 5:00pm
    • HWs should be submitted to the HW box in 283 Soda -- not to Dave or your TA!
    9-3-2003 Important enrollment info:
    • Even though there is lots of space in the class, there is a mistake in Telebears that is preventing us from adding people into sections. Therefore,
    • If you are not enrolled in the course, but want to get in, here is what you have to do: By Friday 9/5 1:00pm, talk to Michael David Sasson (in person) in 379 Soda. Be sure to tell him which section you want to move into. If you don't talk to him by Friday, we can't add you to the class!
    9-1-2003 The submit program now works! Please submit using the intructions in the previous announcement. The submit program will be updated for lab 2.
    8-30-2003 Links to page A-48 and A-49 (syscalls in MIPS) have been uploaded for lab 1 for those students without the 2nd edition of COD. See the lab 1 page.
    8-30-2003 The submit program has not been updated from last year. For lab 1, please submit your program by running m:\bin\submit. When it asks you to select the project/lab, select "Lab 2: MIPS ISA and Broken SPIM." Those of you in the 11-1 section, please pick section 101, and everybody else is section 102. The submit program will be updated for future labs. Please note that you can submit only once, so be sure to submit all your files only when you are finished with the lab.
    8-30-2003 The PRS transmitters are now available in limited numbers at the ASUC bookstore. Please go out and get one as soon as you can -- the store is open during the weekends.
    8-27-2003 Please note that lab 1 has changed slightly (as of 10:40am). If you have already downloaded a copy, you may want to download the new one.
    8-27-2003 Welcome to cs152!
    • Please do the preliminary survey as soon as possible.
    • Course account forms will be handed out in Thursday's lecture. If you can't wait that long, there are a limited number of forms available from Willa in 626 Soda Hall.
    • The website from spring 2003 can be found here.

    © 2003 UCB cs152, http://www-inst.eecs.berkeley.edu/~cs152/
    Last Updated: today Webmaster: cs152@cory.eecs.berkeley.edu