• The bus leaves tomorrow at 8:55AM sharp -- we may wait around until 9:00 for stragglers, but after that we are g o n e !
• This is the current roster for the Xilinx trip. If you are not on it, we don't have you listed as going. If you are listed on it and have changed your mind, please email Jack right away. Also, if you are driving yourself and you are not listed as doing so on the roster, please email Jack as well.
• We will be meeting outside the 2nd floor of Cory at 8:35 AM on Tuesday 11/25. Please don't be late!! If the TAs wake up early enough, we'll have some donuts on the bus for you guys. We will be arriving at Xilinx at 10 AM, and leaving at approximately 3 PM, arriving back at Berkeley around 4 PM.
• If you are driving yourself there, please send an email to Jack at cs152-ta@imail.eecs.berkeley.edu so we know who's going where. Please arrive at Xilinx before 10am, and proceed to the lobby of building 1. Directions to Xilinx can be found here. A campus map of Xilinx is here.

• We've posted our notes from today's review section below. These include solutions to the problems.
• HW4 solutions

• MTII will be held 5:30-8:30pm 11/19/2003 in 1 Leconte
• The review session will be held during Tuesday's lecture.
• You are responible for all material covered up to and including Week 12
• If you can't make the scheduled midterm time, email Kurt immediately.

• The final HW 4 is up.
• It is due Tueday 11/18 -- One day later than usual.

For current and future reference, a project working only in simulation but not on board will be graded lower by half a grade to a full grade. This amount will be determined by your TA, based on the reasons for not being able to go to board. If the reasons are for bad design (latches, combinational loop, etc.), then you will lose more points than you would for other, less obvious reasons.

• We've posted a regrading policy on the info page.
• Solutions and standards for Exam 1 are here.
• Solutions for HW3 are here.

Problem 3, line 2) has been changed from "if either the processor or DRAM is busy with a read-miss" to say "if either the instCache or dataCache is busy with a read-miss."

Your TA will be communicate with you to set up lab 4 demo times on Monday or Tuesday (10/13-14).

• Scores are in glookup.
• 60 students took the exam.
• The mean on the exam was 75.3
• The mean for individual questions was 20.6/30, 27.4/35, and 27.0/35, repsectively.
• More stats have been posted to the newsgroup.
• We'll publish solutions shortly.
• If your login is cs152-cv or cs152-ag and you want a grade for the exam, then you need to log into your class account -- your named account doesn't count.

TopLevel.v has been changed to include a line telling synplify where to find all the Xilinx black boxes.

dll_standard.v has been changed also to use CLKDLLE rather than CLKDLL, since we are using the Virtex-E rather than the Virtex architecture.

We have also replaced the clkdll.v file with the clkdlle.v file. Please note that you should not include the clkdlle.v file in your design, the file is only there for your reference. Instead, you should let synplify treat it as a black box, and let Xilinx take care of it during the partition, place, and route.

• Chapter 1: 1.4, 1.5
• Chapter 2: 2.2-2.6
• Chapter 3: 3.4-3.9
• Chapter 4: 4.1, 4.3-4.5
• Chapter 5: 5.1, 5.3-5.7, 5.8
• Chapter 6: 6.1-6.7

The review session used questions from the Spring 2001 and Spring 2003 Midterm. You can find those and other tests here.

The pipelining question came from the Fall 2003 CS252 prereq exam. You can find that here.

• We are going to be entering grades on the Unix systems, so it is important that your information is accurate.
• Be sure to pick a reasonably secure 'secret code', as this information will be used by the WebGrades system.
• If you forgot your registration information, or you were never asked for it, log into your Unix account and type 're-register'.

Also, please don't forget to include you online notebooks in your lab report, along with a summary at the top of each person's notebook with their total time spent on this lab.

• Use step 2.4b rather than step 2.4 when going from the synplify edif file. If you have already used step 2.4 in the past, start over by recreating a synplify project and going through the steps using 2.4b.
• Make sure you use synplify to synthesize. Do not just click Generate Programming File in Xilinx Design Manager with all of your verilog files there. Xilinx Design Manager will not synthezie the pin outs correctly.
• Check your warnings in synplify! If you have warnings that relate to your logic, that may be your problem

• Due to the learning curve, this may be one of the hardest labs of the semester. Get started early! Students who haven't taken 150 should definitely attend the demo on Friday from 3-4pm.
• The COD Appendices are in the resources page.
• Jack's Lab 2 overview slides are available.

• The due date has been extended to Wed 9/10 at 5:00pm
• HWs should be submitted to the HW box in 283 Soda -- not to Dave or your TA!

• Even though there is lots of space in the class, there is a mistake in Telebears that is preventing us from adding people into sections. Therefore,
• If you are not enrolled in the course, but want to get in, here is what you have to do: By Friday 9/5 1:00pm, talk to Michael David Sasson (in person) in 379 Soda. Be sure to tell him which section you want to move into. If you don't talk to him by Friday, we can't add you to the class!

• Please do the preliminary survey as soon as possible.
• Course account forms will be handed out in Thursday's lecture. If you can't wait that long, there are a limited number of forms available from Willa in 626 Soda Hall.
• The website from spring 2003 can be found here.